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Data Sheet
gate voltage of the external FET. This minimizes the bus supply
voltage drop caused by the fault and protects neighboring cards.
As the voltage across the sense resistor approaches the current
limit, a timer activates. This timer resets again if the sense
V IN
V ON
1
ADM1172
voltage returns below this level. If the sense voltage is any
voltage below 44 mV, the timer is guaranteed to be off. Should
the current continue to increase, the ADM1172 tries to regulate
the gate of the FET to achieve a limit of 50 mV across the sense
resistor. However, if the device is unable to regulate the fault
current and the sense voltage further increases, a larger pull-
down, in the order of milliamperes, is enabled to compensate
for fast current surges. If the sense voltage is any voltage greater
than 56 mV, this pull-down is guaranteed to be on. When the
V TIMER
V GATE
V OUT
2
3
4
timer expires, the GATE pin shuts down.
RESET
MODE
INITIAL
CYCLE
NORMAL
CYCLE
TIMER FUNCTION
The TIMER pin is responsible for several key functions on the
ADM1172 . A capacitor controls the initial power on reset time
and the amount of time an overcurrent condition lasts before
the FET shuts down. On the ADM1172-1 , the timer pin also
controls the time between auto retry pulses. There are pull-up
V IN
START-UP
CYCLE
Figure 38. Power-Up Timing
and pull-down currents internally available to control the timer
functions. The voltage on the TIMER pin is compared with two
V ON
5μA
60μA
2μA
threshold voltages: COMP1 (0.2 V) and COMP2 (1.3 V). The
four timing currents are listed in Table 5.
Table 5.
V TIMER
100μA
Timing Current
Pull-up
Pull-up
Pull-down
Pull-down
Level (μA)
5
60
2
100
V GATE
V OUT
I RSENSE
POWER-UP TIMING CYCLE
The ADM1172 is in reset when the ON (ON-CLR) pin is held
RESET
MODE
INITIAL START-UP
CYCLE CYCLE
NORMAL
CYCLE
low. The GATE pin is pulled low and the TIMER pin is pulled
low with a 100 μA pull-down. At Time Point 2 in Figure 38, the
ON (ON-CLR) pin is pulled high. For the device to startup
correctly, the supply voltage must be above UVLO, the ON
(ON-CLR) pin must be above 1.3 V, and the TIMER pin voltage
must be less than 0.2 V. The initial timing cycle begins when these
three conditions are met, and the TIMER pin is pulled high with
5 μA. At Time Point 3, the TIMER reaches the COMP2 threshold.
This is the end of the first section of the initial cycle. The 100 μA
current source then pulls down the TIMER pin until it reaches
0.2 V at Time Point 4. The initial cycle delay (Time Point 2 to
Time Point 4) relates to C TIMER by equation
Figure 39. Power-Up into Capacitor
t INITIAL = 1.3 × C TIMER /5 μA
(4)
When the initial cycle ends, a start-up cycle activates and the
GATE pin is pulled high; the TIMER pin continues to pull down.
Rev. A | Page 13 of 16
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